Cadence North American University Program 

Portland State University 

Welcome to the Department of Electrical and Computer Engineering, Cadence North American University Software Program at Portland State University. This material and the references within are a first-line source of information about the Cadence design tools extensively used in classes and research programs in the Electrical and Computer Engineering Department. Classes and research span custom transistor level digital and analog design, floorplanning, placement, and routing as well as statistical modeling of process corners, yield, and manufacturability.



Cadence CAE packages are used primarily in senior electives and first-year graduate core courses. The tools are used for independent study projects, theses, and dissertations. 

1. ECE 4/525: Digital Integrated Circuit Design I
This is the first term of an approved two term undergraduate sequence. The first term’s goals are to learn three large signal device models for the MOSFET and use them in simple design problems; to introduce the steps used in MOSFET fabrication and begin the study of CMOS circuit and logic design. A laboratory is integrated into the lecture. Students will gain skills in device and small scale integrated circuit simulation and, CMOS IC layout.

2. ECE 4/526: Digital Integrated Circuit Design II
This is the second term of an approved two term undergraduate sequence and an approved three term graduate sequence. The second term’s goals are to apply the results of last term’s study of MOSFET gates and use them in small design problems; to introduce the steps used in floor-planning of digital subsystems and circuits; and introduce the study of test and manufacturability of digital MOS circuits. A laboratory is integrated into the lecture. Students will gain skills in device and small scale integrated circuit simulation and, CMOS IC layout. Graduate students are encouraged this term to complete an independent design project. The details of the project will be discussed separately.

ECE Students in electrical and computer engineering are introduced to the analysis and design of digital integrated circuits. A design project is an integral part of above 2 courses.

3. ECE 4/528: VLSI Computer Aided-Design I & II 
Introduces basic techniques and algorithms for computer-aided design and optimization of VLSI circuits. The first part discusses VLSI design process flow for custom, ASIC and FPGA design styles and gives an overview of VLSI fabrication with emphasis on interconnections. The necessary background in graph theory and mathematical optimization is introduced. In the second part, application of different analytical and heuristic techniques to physical design (partitioning, placement, floor-planning and routing) of VLSI circuits is studied. We shall emphasize VLSI design issues encountered in deep sub-micron technology. Throughout the course students will be exposed to research methodology and to a set of academic and commercial CAD tools for physical design. Prerequisite: senior or graduate standing.

4. ECE 575/675: Introduction to IC Test
Course will cover the traditional role of IC test parametric and functional testing and the changing role of IC testing in semiconductor design and manufacturing. The course is divided into three parts. The first part reviews integrated circuit technologies and fault modeling. The second introduces digital IC test, DC parametric testing, and functional and structural testing.

5. ECE 4/581: ASIC: Modeling and Synthesis
This course covers the fundamentals of the ASIC design process. The topics include ASIC design Flow, basic HDL constructs, test-benches, modeling combinational & synchronous logic, modeling finite state machines, multiple clock domain designs, qualitative design issues, ASIC constructions.

6. ECE 4/583: Low Power Digital IC Design
Introduction to the existing techniques for IC power modeling, optimization, and synthesis. Topics include: sources of power dissipation, design for low power, voltage scaling approaches, power analysis techniques, power optimization techniques, low-power system-level designs. Focus on abstraction, modeling, and optimization at all levels of design hierarchy, including the technology, circuit, layout, logic, architectural, and algorithmic levels. Prerequisite: ECE 425/525

7. ECE 527/627 - High-Performance Digital System 
The use of computer-aided design tools in high-performance digital systems is explored. The trade-offs between automated and hand design are examined in the context of performance vs. development time. The impact of new developments in MOS circuit technology are also examined. Prerequisite: ECE 426/526

Cadence Setup

The materials on this website are developed for the Electrical and Computer Engineering VLSI Design Laboratory at Portland State University. The ECE VLSI Design Laboratory is home to two Linux servers and Accounts are available to students registered for ECE prefix courses. If you are new to PSU please familiarize yourself with computer account procedures and policies. The ECE VLSI Design Laboratory provides the Cadence software via the Cadence North America University Software Program. The base Cadence software is configured to support MOSIS TSMC design rules and models using the North Carolina State Cadence Design Kit (NCSU CDK).


Below are some helpful resources for using Cadence products at PSU:

PSU Cadence Wiki

Cadence Wiki Pages provide some screen shots and a short description of what the basic steps to create and simulate a CMOS design at the transistor schematic level. The Cadence IC615 distribution (and the appearance of some of the windows) is not the one used when the tutorials were recorded Fall 2012.

NCSU Cadence Design Kit

The NCSU Cadence Design Kit configures the Cadence software, provides technology specific data and additional menu options. The course laboratories and the tutorials provided in the tutorial sections are designed with the NCSU CDK configuration. You must collect a tar file for a set of scripts to set binary paths and the like before design and simulation of the circuits. Tutorials from NCSU describe many of the basic steps. Some tutorials are for tools not used in Portland State courses.


In addition to the NCSU Cadence Design Kit FreePDK45 is a nominal 45nm transistor. The FreePDKTM process design kit is an open-source, Open-Access-based PDK for the 45nm technology node.


Information is provided "as is" without warranty of any kind. Anyone may use information available from this web-site and all use of the information gathered from this web-site is at the user’s own risk. Before using the provided materials on any data create data backups within the user environment. Creating backups and the backup frequency are user responsibilities. It is the user’s responsibility is to understand what each distributed component does. Keep data backups intact. Delete backups at own risk and only when satisfied with results.


    This site is maintained by Bill Attebury,                                                                                                                                Cadence is a registered trademark of

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    This site last updated on January 5, 2018.                                                                                                                                                       2655 Seely Avenue   

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