Electrical and Computer Engineering / Cadence North American University Program
Portland State University
Academic Year 2014-2015

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Welcome to the Department of Electrical and Computer Engineering, Cadence North American University Software Program at Portland State University. This material and the references within are a first-line source of information about the Cadence design tools extensively used in classes and research programs in the Electrical and Computer Engineering Department. Classes and research span custom transistor level digital and analog design, floorplanning, placement and route as well as statistical modeling of process corners, yield and manufacturability.

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Cadence CAE packages are used primarily in senior electives and first year graduate core courses. The tools are used for independent study projects, thesis and dissertations. Custom, semi-custom and PCB design flows are used and generally are based on the North Carolina State Cadence Design Kit. and the Cadence design flows from Oklahoma State University

ECE 425/426, ECE Students in electrical and computer engineering are introduced to the analysis and design of digital integrated circuits. A design project is an integral part of this course.

ECE 528/529, VLSI Computer Aided Design I&II: Introduces basic techniques and algorithms for computer-aided design and optimization of VLSI circuits. The first part discusses VLSI design process flow for custom, ASIC and FPGA design styles and gives an overview of VLSI fabrication with emphasis on interconnections. The necessary background in graph theory and mathematical optimization is introduced. In the second part, application of different analytical and heuristic techniques to physical design (partitioning, placement, floor-planning and routing) of VLSI circuits is studied. We shall emphasize VLSI design issues encountered in deep sub-micron technology. Throughout the course students will be exposed to research methodology and to a set of academic and commercial CAD tools for physical design. Prerequisite: senior or graduate standing.

ECE 575, Introduction to IC Test: Course will cover the traditional role of IC test parametric and functional testing and the changing role of IC testing in semiconductor design and manufacturing. The course is divided into three parts. The first part reviews integrated circuit technologies and fault modeling. The second introduces digital IC test, DC parametric testing, and functional and structural testing.

Course not offered in Fall 2007.

ECE 481/581 ASIC: Modeling and Synthesis: This course covers the fundamentals of the ASIC design process. The topics include ASIC design Flow, basic HDL constructs, test-benches, modeling combinational & synchronous logic, modeling finite state machines, multiple clock domain designs, qualitative design issues, ASIC constructions.

ECE 483/583 LOW POWER DIGITAL IC DESIGN: Introduction to the existing techniques for IC power modeling, optimization, and synthesis. Topics include: sources of power dissipation, design for low power, voltage scaling approaches, power analysis techniques, power optimization techniques, low-power system-level designs. Focus on abstraction, modeling, and optimization at all levels of design hierarchy, including the technology, circuit, layout, logic, architectural, and algorithmic levels. Prerequisite: ECE 425/525

ECE 527/627 HIGH-PERFORMANCE DIGITAL SYSTEMS: The use of computer-aided design tools in high-performance digital systems is explored. The trade-offs between automated and hand design are examined in the context of performance vs. development time. The impact of new developments in MOS circuit technology are also examined. Prerequisite: ECE 426/526


Information is provided "as is" without warranty of any kind. Please follow the link to read the full text of the disclaimer.

[close] PSU VLSI Laboratory and Cadence Setup

NCSU Cadence Design Kit
PSU Cadence Wiki


The materials on this web-site are developed for the Electrical and Computer Engineering VLSI Design Laboratory at Portland State University. The ECE VLSI Design Laboratory is home to two Linux servers eve.ece.pdx.edu and walle.ece.pdx.edu.

Accounts are available to students registered for ECE prefix courses. If you are new to PSU please familiarize yourself with computer account procedures and policies.

The ECE VLSI Design Laboratory provides the Cadence software via the Cadence North America University Software Program. The base Cadence software is configured to support MOSIS TSMC design rules and models using the North Carolina State Cadence Design Kit (NCSU CDK).

NCSU Cadence Design Kit

The NCSU Cadence Design Kit configures the Cadence software, provides technology specific data and additional menu options. The course laboratories and the tutorials provided in the tutorial sections are designed with the NCSU CDK configuration. You must collect a tar file for a set of scripts to set binary paths and the like before design and simulation of the circuits. Tutorials from NCSU describe many of the basic steps. Some tutorials are for tools not used in Portland State courses.


In addition to the NCSU Cadence Design Kit FreePDK45 is a nominal 45nm transistor. The FreePDKTM process design kit is an open-source, Open-Access-based PDK for the 45nm technology node.

PSU Cadence Wiki

Cadence Wiki Pages provide some screen shots and a short description of what the basic steps to create and simulation a CMOS design at the transistor schematic level.

The Cadence IC615 distribution (and the appearance of some of the windows) is not the one used when the tutorials were recorded Fall 2012.

A student composed two MP4 videos outlining the basic steps to complete the design of a CMOS inverters using the Cadence Design Tools. The first tutorial relates to schematics and the second is physical design of the inverter.

Inverter Schematic Design

Inverter Physical Design



Do not edit the files. The Cadence tools will edit your files as you create libraries and complete design assignments.

Do not move the files from the ./cadence subdirectory

Do not reextract the tarball or git restore the ./cadence directory after the first use of the Cadence tools. A reinstall requires careful preservation of specific files. Be careful.


Information is provided "as is" without warranty of any kind. Please follow the link to read the full text of the disclaimer.

[open] Other IC Design URLs

[open] Disclaimer

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PSU Cadence North American University Administrator c-nausp@ece.pdx.edu
Created: Oct 31, 2014