Electrical and Computer Engineering / Cadence North American University Program
Portland State University
Academic Year 2014-2015

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Welcome to the Department of Electrical and Computer Engineering, Cadence North American University Software Program at Portland State University. This material and the references within are a first-line source of information about the Cadence design tools extensively used in classes and research programs in the Electrical and Computer Engineering Department. Classes and research span custom transistor level digital and analog design, floorplanning, placement and route as well as statistical modeling of process corners, yield and manufacturability.

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Cadence CAE packages are used primarily in senior electives and first year graduate core courses. The tools are used for independent study projects, thesis and dissertations. Custom, semi-custom and PCB design flows are used and generally are based on the North Carolina State Cadence Design Kit. and the Cadence design flows from Oklahoma State University

ECE 425/426, ECE Students in electrical and computer engineering are introduced to the analysis and design of digital integrated circuits. A design project is an integral part of this course.

ECE 528/529, VLSI Computer Aided Design I&II: Introduces basic techniques and algorithms for computer-aided design and optimization of VLSI circuits. The first part discusses VLSI design process flow for custom, ASIC and FPGA design styles and gives an overview of VLSI fabrication with emphasis on interconnections. The necessary background in graph theory and mathematical optimization is introduced. In the second part, application of different analytical and heuristic techniques to physical design (partitioning, placement, floor-planning and routing) of VLSI circuits is studied. We shall emphasize VLSI design issues encountered in deep sub-micron technology. Throughout the course students will be exposed to research methodology and to a set of academic and commercial CAD tools for physical design. Prerequisite: senior or graduate standing.

ECE 575, Introduction to IC Test: Course will cover the traditional role of IC test parametric and functional testing and the changing role of IC testing in semiconductor design and manufacturing. The course is divided into three parts. The first part reviews integrated circuit technologies and fault modeling. The second introduces digital IC test, DC parametric testing, and functional and structural testing.

Course not offered in Fall 2007.

ECE 481/581 ASIC: Modeling and Synthesis: This course covers the fundamentals of the ASIC design process. The topics include ASIC design Flow, basic HDL constructs, test-benches, modeling combinational & synchronous logic, modeling finite state machines, multiple clock domain designs, qualitative design issues, ASIC constructions.

ECE 483/583 LOW POWER DIGITAL IC DESIGN: Introduction to the existing techniques for IC power modeling, optimization, and synthesis. Topics include: sources of power dissipation, design for low power, voltage scaling approaches, power analysis techniques, power optimization techniques, low-power system-level designs. Focus on abstraction, modeling, and optimization at all levels of design hierarchy, including the technology, circuit, layout, logic, architectural, and algorithmic levels. Prerequisite: ECE 425/525

ECE 527/627 HIGH-PERFORMANCE DIGITAL SYSTEMS: The use of computer-aided design tools in high-performance digital systems is explored. The trade-offs between automated and hand design are examined in the context of performance vs. development time. The impact of new developments in MOS circuit technology are also examined. Prerequisite: ECE 426/526


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Information is provided "as is" without warranty of any kind. Anyone may use information available from this web-site and all use of the information gathered from this web-site is at the user’s own risk. Before using the provided materials on any data create data backups within the user environment. Creating backups and the backup frequency are user responsibilities. It is the user’s responsibility is to understand what each distributed component does. Keep data backups intact. Delete backups at own risk and only when satisfied with results.

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PSU Cadence North American University Administrator c-nausp@ece.pdx.edu
Created: Oct 31, 2014