Welcome to the Department of Electrical and Computer Engineering, Cadence North American University Software Program at Portland State University. This material and the references within are a first-line source of information about the Cadence design tools extensively used in classes and research programs in the Electrical and Computer Engineering Department. Classes and research span custom transistor level digital and analog design, floorplanning, placement and route as well as statistical modeling of process corners, yield and manufacturability.
The materials on this web-site are developed for the Electrical and Computer Engineering VLSI Design Laboratory at Portland State University. The ECE VLSI Design Laboratory is home to two Linux servers eve.ece.pdx.edu and walle.ece.pdx.edu.
Accounts are available to students registered for ECE prefix courses. If you are new to PSU please familiarize yourself with computer account procedures and policies.
The ECE VLSI Design Laboratory provides the Cadence software via the Cadence North America University Software Program. The base Cadence software is configured to support MOSIS TSMC design rules and models using the North Carolina State Cadence Design Kit (NCSU CDK).
The NCSU Cadence Design Kit configures the Cadence software, provides technology specific data and additional menu options. The course laboratories and the tutorials provided in the tutorial sections are designed with the NCSU CDK configuration. You must collect a tar file for a set of scripts to set binary paths and the like before design and simulation of the circuits. Tutorials from NCSU describe many of the basic steps. Some tutorials are for tools not used in Portland State courses.
In addition to the NCSU Cadence Design Kit FreePDK45 is a nominal 45nm transistor. The FreePDKTM process design kit is an open-source, Open-Access-based PDK for the 45nm technology node.
Cadence Wiki Pages provide some screen shots and a short description of what the basic steps to create and simulation a CMOS design at the transistor schematic level.
The Cadence IC615 distribution (and the appearance of some of the windows) is not the one used when the tutorials were recorded Fall 2012.
A student composed two MP4 videos outlining the basic steps to complete the design of a CMOS inverters using the Cadence Design Tools. The first tutorial relates to schematics and the second is physical design of the inverter.
Inverter Schematic Design
Inverter Physical Design
Do not edit the files. The Cadence tools will edit your files as you create libraries and complete design assignments.
Do not move the files from the ./cadence subdirectory
Do not reextract the tarball or git restore the ./cadence directory after the first use of the Cadence tools. A reinstall requires careful preservation of specific files. Be careful.
Information is provided "as is" without warranty of any kind. Please follow the link to read the full text of the disclaimer.
Information is provided "as is" without warranty of any kind. Anyone may use information available from this web-site and all use of the information gathered from this web-site is at the user’s own risk. Before using the provided materials on any data create data backups within the user environment. Creating backups and the backup frequency are user responsibilities. It is the user’s responsibility is to understand what each distributed component does. Keep data backups intact. Delete backups at own risk and only when satisfied with results.